Xilinx, Inc. the assignee of the present application, manufactures logic devices. Although some devices are mask programmable, many devices manufactured by Xilinx are field programmable logic devices. A programmable logic device is an integrated circuit chip which includes a plurality of programmable input/output pads, a plurality of configurable logic elements, and a programmable interconnect for interconnecting the plurality of logic elements. Further, each logic element includes a logic block which implements a logic function of the n inputs to the logic block according to how the logic element has been configured. Logic functions may use all n inputs to the logic block or may use only a subset thereof. A few of the possible logic functions that a logic element can be configured to implement are: AND, OR, XOR, NAND, NOR, NXOR and mixed combinations of these functions. The implementation and operation of logic devices made by Xilinx are described in "The Programmable Logic Data Book," pages 4-1 to 4-372, copyright 1996 by Xilinx, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. The contents of "The Programmable Logic Data Book" are incorporated herein by reference.
As the density of logic devices increases, the complexity of possible designs that can be incorporated into a single device increases. By reusing existing designs from previous projects, designers are freed from having to "recreate the wheel", and are better able to concentrate on the new aspects of their designs. Designers have created libraries of designs which represent previously tested designs, but these known libraries were not automatically extendable to designs using a larger number of bits or designs with slightly different parameters. For example, known libraries included designs for each bit size of a particular type of component, e.g., adders from a single-bit adder to a thirty-two-bit adder. By including each of these designs separately, library sizes grew quickly. In static library configurations, despite the large library sizes, extending a library is awkward and involves using a library component along with design specific logic to create a custom piece, e.g., combining a single-bit adder with a thirty-two-bit adder to create a thirty-three-bit adder. This restrictive design methodology which creates large libraries and semi-rigid designs is not easily adaptable to an increasingly dynamic design schedule which requires faster turn-around times for designs. Likewise, libraries which include statically pre-routed components are not adaptable to changes in architecture or to a variation in shape of the unused components of an architecture.
To help decrease design time, designers have turned to two important technologies: 1) programmable gate arrays and 2) hardware description languages. Gone are the days of hardwired discrete components being used to implement circuits for printed circuit board-level designs. Designers now use compact, highly integrated, VLSI chips to conserve board space and system power. However, fabricating an ASIC also requires an increase in lead time to fabricate and test the ASIC to be used in a design. Xilinx sells a family of field programmable gate arrays (FPGAs) that can be quickly programmed and reprogrammed by a designer to implement a particular logic function. Using FPGA-based boards, changes can be made to a design by simply reprogramming the appropriate FPGA, without even removing the FPGA from its socket. This technique reduces design time.
The use of hardware description languages also reduces design time. Although schematic capture was previously used to develop designs, hardware description languages such as VHDL are now capable of generating designs from logical descriptions of the functions which are to be performed by the circuit being built. It is believed that this more generalized and higher level approach allows designs to be created more compactly and to be analyzed more quickly. A hardware description language is then compiled like a high-level programming language to produce a design file which implements the specifics of the design. This design file is either an intermediate design file which is architecture independent, or it is a product specific design file, e.g., a design file specific to a gate array architecture or a FPGA architecture. When generating a product specific design file, the design compiler determines routes between independent units in the design, and as the number of independently routed units increases, so does the time required to generate a new or modified design. Synopsys, Inc. of 700 East Middlefield Rd. in Mountain View, Calif., provides a suite of tools which support hardware description languages. Tools produced by Synopsys, Inc. include DesignWare and FPGA Express. Details on DesignWare can be found in the January 1996, April 1996, July 1996 and October 1996 editions of the DesignWare Technical Bulletin. The contents of each of these Technical bulletins is incorporated herein by reference. However, a significant limitation of DesignWare is that it does not support user-specific, parameterized attributes which can be converted to properties of instances of components.